Carbon nanostructure device fabrication utilizing protect layers

ABSTRACT

Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

GOVERNMENT CONTRACT

This invention was made with Government support under Contract No.FA8650-08-C-7838 awarded by Defense Advanced Research Projects Agency(DARPA). The Government has certain rights in this invention.

BACKGROUND

The present invention relates to Hall effect devices and field effecttransistors (FETs) incorporating a carbon-based nanostructure layer, andmore specifically, to Hall effect and FET devices incorporatinghigh-carrier mobility carbon-based nanostructure layers patterned bymethods utilizing inorganic sacrificial channel protect layers.

The integration of carbon-based nanostructures as channel materials inthe next generation of electronic devices offers many advantages overthe continued scaling of silicon (Si). Carbon nanotubes (CNT's) andgraphene are two nanoscale forms of carbon that exhibit extremely highcurrent carrying capacity and mobilities several orders of magnitudebeyond the theoretical limit for Si. Additionally, CNTs (1 dimension)and graphene (2 dimensions) are low-dimensional (ultra thin-body)materials, allowing them to be aggressively scaled in field-effecttransistors without incurring deleterious short-channel effects thatplague modern scaled devices.

BRIEF SUMMARY OF THE INVENTION

Described here are CNT and graphene device structures and methods ofmaking that utilize sacrificial channel-protect layers to keep the CNTor graphene from being exposed to undesirable organic moieties presentduring resist processing steps. The methods may be employed to fabricatea variety of CNT or graphene devices including Hall bars, gated Hallbars, and field effect transistors (FETs).

In accordance with the present invention, a method is provided forforming a device structure, the method comprising selecting aninsulating substrate having a carbon-based nanostructure layer on anupper surface; forming a first layer of a first metal on thecarbon-based nanostructure layer; forming a first patterned layer havinga first pattern on the first layer of first metal; transferring thefirst pattern to the first layer of a first metal and the carbon-basednanostructure layer to form a first patterned layer of a first metal anda first patterned carbon-based nanostructure layer there under; removingthe first patterned layer; forming a second patterned layer of a secondmetal over the insulating substrate and the first patterned layer of afirst metal, the second patterned layer of a second metal having asecond pattern comprising a plurality of contacts spaced apart from oneanother wherein respective contacts have a portion on the firstpatterned layer of a first metal and a portion on the insulatingsubstrate; and removing the first patterned layer of a first metal wherenot covered by the plurality of contacts whereby the first patternedcarbon-based nanostructure layer has regions not covered by the firstpatterned layer of first metal.

The invention further provides a device structure comprising aninsulating substrate; a first patterned layer of carbon-basednanostructure layer on the substrate; a first patterned layer of a firstmetal on the first patterned carbon-based nanostructure layer; and aplurality of spaced apart contacts having a portion on the patternedmetal layer and a portion on the insulating substrate; the firstpatterned carbon-based nanostructure layer having regions not covered bythe first patterned layer of a first metal.

The invention further provides a method for forming a device structurecomprising selecting an insulating substrate having a carbon-basednanostructure layer on an upper surface; forming a first layer of afirst metal on the carbon-based nanostructure layer; forming a firstpatterned layer having a first pattern on the first layer of a firstmetal; transferring the first pattern to the first layer of a firstmetal and the carbon-based nanostructure layer to form a first patternedlayer of a first metal and a first patterned carbon-based nanostructurelayer there under; removing the first patterned layer; forming a layerof first material over the insulating substrate and the first patternedlayer of a first metal, the layer of first material reactive with thefirst patterned layer of a first metal when raised to a predeterminedtemperature; optionally forming a layer of second material over thelayer of first material; the layer of second material providing anelectrically conductive diffusion barrier with respect to the layer offirst material; forming a second layer of metal over the layer of secondmaterial; patterning the second layer of metal, the layer of secondmaterial, and the layer of first material to form source and drainregions spaced apart wherein respective regions have a portion on thepatterned metal and a portion on the insulating substrate; heating thelayer of first material on the patterned first metal to cause a reactionthere between for forming a reacted region of one of a chemical compoundand an alloy; and selectively removing unreacted patterned first metalto expose the patterned carbon-based nanostructure layer between thesource region and the drain region.

The invention also includes the aforementioned methods in combinationwith additional steps for gate dielectric and gate formation, tofabricate, for example, gated Hall structures and FET devicesincorporating high-carrier mobility carbon-based nanostructure layers.The invention also includes the aforementioned methods implemented oninsulating substrates that include at least one embedded gate with agate dielectric layer thereupon, to fabricate, for example bottom gateor dual gate FET devices incorporating high-carrier mobilitycarbon-based nanostructure layers.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

These and other features, objects, and advantages of the presentinvention will become apparent upon consideration of the followingdetailed description of the invention when read in conjunction with thedrawing in which:

FIG. 1 is a top view of a structure comprising an insulating basesubstrate, a carbon-based nanostructure layer on the base substrate, anda metal layer on the carbon-based nanostructure layer.

FIG. 2 is a cross-section view along the lines 2-2 of FIG. 1.

FIG. 3 is a top view of the substrate of FIG. 1 after patterning of themetal layer and carbon-based nanostructure layer.

FIG. 4 is a cross-section view along the lines 4-4 of FIG. 3.

FIG. 5 is a top view of an intermediate structure.

FIG. 6 is a cross-section view along the lines 6-6 of FIG. 5.

FIG. 7 is a top view of a Hall effect device.

FIG. 8 is a cross-section view along the lines 8-8 of FIG. 7.

FIG. 9 is a top view of a patterned mask.

FIG. 10 is a cross-section view along the lines 10-10 of FIG. 9.

FIG. 11 is a top view of a patterned mask after etching.

FIG. 12 is a cross-section view along the lines 12-12 of FIG. 11.

FIG. 13 is a top view of a patterned metal layer, carbon-basednanostructure layer and substrate.

FIG. 14 is a cross-section view along the lines 14-14 of FIG. 13.

FIG. 15 is a top view of an intermediate structure of an FET.

FIG. 16 is a cross-section view along the lines 16-16 of FIG. 15.

FIG. 17 is a top view of an intermediate structure of an FET.

FIG. 18 is a cross-section view along the lines 18-18 of FIG. 17.

FIG. 19 is a top view of a FET.

FIG. 20 is a cross-section view along the lines 20-20 of FIG. 19.

FIG. 21 is a cross-section view of an intermediate structure showing adielectric layer on the top and sidewalls of a source and drain of a FETand yet absent from graphene in the channel region.

FIG. 22 is a cross-section view of an intermediate structure showing adielectric layer on the top of a source and drain of a FET.

FIG. 23 is a cross-section view of an intermediate structure showing thecombination of the dielectric layers of FIGS. 21 and 22

FIG. 24 is a cross-section view of an FET incorporating a single-partsource and drain and using the extra dielectric layer of FIG. 22.

FIG. 25 is a cross-section view of an FET incorporating a two-partsource and drain comprising extension regions and using the extradielectric layer of FIG. 22.

FIGS. 26-31 are cross-section views illustrating the process flow forforming an FET with a one-part source and drain, no additional sourceand drain dielectric, and reacted channel-protect residuals for the caseof a conductive reactive layer.

FIGS. 32-37 are cross-section views illustrating the process flow forforming an FET with a multilayer one-part source and drain, noadditional source and drain dielectric, and reacted channel-protectresiduals for the case of an insulating reactive layer.

FIGS. 38-43 are cross-section views illustrating the process flow forforming an FET with a two-part source and drain comprising source anddrain pads and source and drain extension regions, additional top sourceand drain dielectric, and reacted channel-protect residuals.

FIG. 44 is a cross-section view of a FET showing a gate dielectricextending beyond the bottom gate electrode and a carbon-basednanostructure layer.

FIG. 45 is a cross-section view of a FET showing a gate dielectricpatterned to cover the bottom gate electrode.

FIG. 46 is a cross-section view of a double gate FET showing the lowergate dielectric extending beyond the bottom gate electrode and acarbon-based nanostructure layer.

FIG. 47 is a cross-section view of a double gate FET showing the lowergate dielectric patterned to cover the bottom gate electrode.

DETAILED DESCRIPTION

Referring now to the drawings, FIGS. 1-8 show top views and crosssection views of intermediate and final structures of a Hall effectdevice having a Hall bar structure. FIG. 1 shows a top view ofsacrificial metal layer 14 which functions to protect an upper surface22 of carbon-based nanostructure layer 20 shown in FIG. 2 fromcontamination such as from hydrocarbons and other contamination. FIG. 2is a cross section view along the lines 2-2 of FIG. 1. For example,contamination of upper surface 22 of carbon-based nanostructure layer 20may come from residuals of a photoresist used to pattern carbon-basednanostructure layer 20. Structure 12 comprises an insulating substrate16, a carbon-based nanostructure layer 20 and sacrificial metal layer14. Sacrificial metal layer 14 is referred to as sacrificial becausesignificant portions of sacrificial metal layer 14 are present onlytemporarily and are intended for subsequent removal. Insulatingsubstrate 16 may be for example SiC, or SiO₂ over Si. Insulatingsubstrate 16 has an upper surface 18. Carbon-based nanostructure layer20 is formed or positioned on upper surface 18. Carbon-basednanostructure 20 has an upper surface 22 and may be selected from thegroup consisting of carbon-nanotubes and graphene. Sacrificial metallayer 14 is formed on upper surface 22 of carbon-based nanostructurelayer 20. Sacrificial metal layer 14 may be selected from the groupconsisting of Ni, Pd, Cu, and other metals.

A first patterned layer (not shown) such as a photoresist having a firstpattern 23 is formed on sacrificial metal layer 14. First patternedlayer may be patterned by photolithography, for example, by aphotoresist which is exposed with light passing through a maskcontaining first pattern 23. The photoresist is subsequently developed.First pattern 23 is then transferred to sacrificial metal layer 14 andto carbon-based nano structure layer 20 to form first patternedsacrificial metal 24 and first patterned carbon-based nanostructurelayer 26 shown in FIGS. 3 and 4.

FIG. 3 is a top view of patterned sacrificial metal layer 24. FIG. 4 isa cross-section view along the lines 4-4 of FIG. 3. Patternedsacrificial metal layer 24 has an upper surface 25 and functions both asan etching mask and to protect the upper surface 22 of first patternedcarbon-based nanostructure layer 26. Carbon-based nanostructure layer 26is preferably etched with an etchant selective to insulating substrate16. Etching is typically performed by reactive ion etching (RIE), plasmaetching, ion beam etching, or sputter etching in a working gas. Theworking gas may be a single gas or a mixture of gases and is typicallyan oxygen-containing gas.

FIG. 5 is a top view of the structure of FIG. 3 after a plurality ofmetal contacts 31-38 spaced apart from one another has been formed suchas by an additive process consisting of blanket metal deposition onto apatterned photoresist lift-off stencil (not shown) followed by removalof the lift-off stencil and overlying metal; or a subtractive processconsisting of metal layer deposition, formation of a patternedphotoresist mask on the metal layer, followed by removal of exposedregions of the metal layer to form a plurality of contacts 31-38. Thepatterned photoresist mask is subsequently removed. FIG. 6 is a crosssection view along the lines 6-6 of FIG. 5. As shown in FIG. 6, contacts33 and 37 have a portion on upper surface 25 of patterned sacrificialmetal layer 24 and a portion on upper surface 18 of insulating substrate16. Contacts 31, 32, 34-36 and 38 likewise have a portion on uppersurface 25 of patterned sacrificial metal layer 24 and a portion onupper surface 18 of insulating substrate 16.

FIG. 7 is a top view of Hall bar structure 44 after patternedsacrificial metal layer 24 is etched with an etchant selective tocarbon-based nanostructure layer 26. Plurality of contacts 31-38function as a mask during etching. The etchant removes the patternedsacrificial metal layer 24 where not covered by plurality of contacts31-38 leaving regions of insulating substrate 16 and first patternedcarbon-based nanostructure layer 26 exposed where not covered by firstpatterned sacrificial metal layer 24.

FIG. 8 is a cross-section view along the lines 8-8 of FIG. 7. Remainingportions 43 and 47 of patterned sacrificial metal layer 24 remain undercontacts 33 and 37 as shown in FIG. 8. Additional remaining portions offirst patterned sacrificial metal layer 24 also remain under contacts31, 32, 34-36 and 38. The metal selected for first patterned sacrificialmetal layer 24 should provide low contact resistance such as below 1e-05ohm cm² to respective contacts 31-38 and to first patterned carbon-basednanostructure layer 26.

Alignment marks (not shown in FIGS. 1-8) are typically utilized tofacilitate subsequent alignment of masks during patterning. FIGS. 9-14illustrate a method for forming alignment marks in structure 12 shown inFIGS. 1 and 2. Starting with structure 12 of FIGS. 1 and 2, photoresistlayer 50 is formed on upper surface 15 of sacrificial layer 14 andpatterned to provide two spaced apart alignment mark openings 52 and 54such as squares in photoresist layer 50, as shown in top view in FIG. 9.Sacrificial metal layer 14 is shown at the bottom of alignment markopenings 52 and 54. FIG. 10 is a cross-section view along the lines10-10 of FIG. 9 showing alignment mark openings 52 and 54.

FIG. 11 is a top view showing alignment marks 56 and 58 in photo resistlayer 50, carbon-based nanostructure layer 20′ (shown in FIG. 12) andextending into insulating substrate 16′. FIG. 12 is a cross-section viewalong the lines 12-12 of FIG. 11. An etchant is used to extend alignmentmark openings 52 and 54 through sacrificial layer 14′, carbon-basednanostructure layer 20′ and into insulating substrate 16′ to formalignment marks 56 and 58. FIG. 13 is a top view of sacrificial metallayer 14′ after photoresist layer 50 has been removed. FIG. 14 is across-section view along the lines 14-14 of FIG. 13 showing alignmentmarks 56 and 58. Further processing such as shown by FIGS. 3-8 may beperformed where the alignment marks aid in pattern alignment.

FIG. 15 is a top view of an intermediate structure 60 of a field effecttransistor. FIG. 16 is a cross section view along the lines 16-16 ofFIG. 15. The process steps needed to form intermediate structure 60correspond to the processes described with regard to FIGS. 1-8. In FIGS.15 and 16, an insulating substrate 16 having a first patternedcarbon-based nanostructure layer 26′ thereon is shown. First patternedcarbon-based nanostructure layer 26′ has an upper surface 22 withremaining portion 43 of patterned sacrificial metal layer 24 thereon.Source 64 and drain 66 are similar to contacts 33 and 37 shown in FIG.8. A gate dielectric layer 70 is formed over insulating substrate 16,source 64, first patterned carbon-based nanostructure layer 26′ anddrain 66. Gate dielectric layer 70 may be selected from the groupconsisting of the oxides and insulating oxynitrides of Si; oxides andinsulating oxynitrides of metals such as Al, Hf, Y and other metals andtheir mixtures; the above oxides and oxynitrides used with an underlyingbuffer or seed layers such as an organic seed layer made from aderivative of polyhydroxystyrene (the polymer NFC 1400-3CP manufacturedby JSR Micro, Inc., 1280 Mathilda Ave., Sunnyvale, Calif.).

FIG. 17 is a top view of field effect transistor 72 comprisingintermediate structure 60 shown in cross-section in FIG. 18 and apatterned conductive gate electrode 76 on gate dielectric layer 70. FIG.18 is a cross-section view along the lines 18-18 of FIG. 17. Gateelectrode 76 may be patterned by an additive process (e.g., lift-off) ora subtractive process (gate layer deposition followed by gate layerremoval in selected areas). Gate electrode 76 may comprise any suitablemetal or combinations of metals, for example, Ti/Au (e.g., 5 nm of Tifollowed by 25 nm of Au), Cr/Au, Ti/Pd/Au, etc.

FIG. 19 is a top view of field effect transistor 72′. FIG. 20 is across-section view along the lines 20-20 of FIG. 19. At least someportions of gate dielectric layer 70 over source 64 and drain 66 wouldtypically be removed to facilitate subsequent electrical contacts toconductive interconnect structures. In FIGS. 19 and 20, gate dielectriclayer 70 is shown as removed in all regions where not under gateelectrode 76, for example, by a process in which gate electrode 76 isused as a mask during gate dielectric etching.

FIGS. 21-23 are cross-section views of alternative intermediatestructures which may be used in place of intermediate structure 60 inFIG. 16 where dielectric layers 82, 88, or 88 and 82′ are formed toreduce capacitance to the gate electrode 96 shown in FIG. 24. Incontrast to intermediate structure 60 of FIG. 16, which is shown incross section taken through lines 16-16 in FIG. 15, cross-section viewsof alternative intermediate structures 80, 86, and 89 are shown througha line passing from source to drain, though the channel. FIGS. 21-23 maybe completed according to the steps shown in FIGS. 17-20 where a gateelectrode is formed and the gate dielectric is selectively removed. FIG.21 is a cross-section view of intermediate structure 80 showing adielectric layer 82 on the top and sidewalls on source 64 and drain 66of a field effect transistor to be formed. Dielectric layer 82 isselective to carbon-based nanostructure layer 26′ in that it forms onsource 64 and drain 66 and remaining portion 43 but not on carbon-basednanostructure layer 26′. Dielectric layer 82 functions to provideadditional dielectric spacing (that is, in addition to gate dielectriclayer 94 shown in FIG. 24) to space source 64 and drain 66 from a gateelectrode 96 shown in FIG. 24, thereby reducing source 64 and drain 66capacitance to the gate electrode 96.

FIG. 22 is a cross-section view of an intermediate structure 86 showinga dielectric layer 88 on the upper surface of source 64 and drain 66 ofa field effect transistor to be formed. Dielectric layer 88 and thelayer of metal used to form source 64 and drain 66 are preferablypatterned using the same second patterned layer or mask by an additiveor subtractive process. Dielectric layer 88 functions to provideadditional dielectric spacing (that is, in addition to gate dielectriclayer 94 shown in FIG. 24) to space source 64 and drain 66 from gateelectrode 96 shown in FIG. 24, thereby reducing source 64 and drain 66capacitance to the gate electrode 96.

FIG. 23 is a cross-section view of an intermediate structure 89 showingthe combination of dielectric layer 82 shown in FIG. 21 and dielectriclayer 88 shown in FIG. 22. Dielectric layer 82′ is over dielectric layer88. Dielectric layer 82′ and dielectric layer 88 function to provideadditional dielectric spacing (that is, in addition to gate dielectriclayer 94 shown in FIG. 24) to space source 64 and drain 66 from gateelectrode 96 shown in FIG. 24, thereby reducing source 64 and drain 66capacitance to gate electrode 96.

By way of example, FIG. 24 is a cross-section view of a field effecttransistor 90 incorporating a single-part source and drain and extradielectric layer 88 shown in FIG. 22 to reduce capacitance betweensource 64 and gate electrode 96 and between drain 66 and gate electrode96. In FIG. 24 starting with the intermediate structure 86 shown in FIG.22, a gate dielectric 94 is formed over dielectric layer 88, and firstpatterned carbon-based nanostructure layer 26′. Gate electrode 96 isformed over gate dielectric 94. Gate electrode 96 may be formed by anadditive or subtractive process. These same process steps (alsodescribed in connection with FIGS. 17-20) may also be used to form fieldeffect transistors from intermediate structures 80, 86, and 89 of FIGS.21-23.

FIG. 25 is a cross-section view of a field effect transistor 102comprising a two-component source and drain. Compared to FIG. 24, source104 and drain 106 are thinner than source 64 and drain 66 in FIG. 24.Dielectric layer 88′ is formed thicker in FIG. 25 than dielectric layer88 in FIG. 24 to reduce gate electrode 96 capacitance to source 104 anddrain 106. Openings 108 and 110 shown in FIG. 25 containing sourcecontact 112 and drain contact 114, respectively, are formed in gatedielectric 94 and dielectric layer 88′ to expose the upper surface ofsource 104 and drain 106. Patterned source contact 112, drain contact114, and gate electrode 96 may be formed at the same time, concurrently,by an additive process such as lift-off or a subtractive process such asmetal layer deposition and etching through a mask. While source anddrain contacts 112 and 114 are not shown as directly abutting dielectriclayer 88′, one or both of these contacts may be slightly spaced apartfrom dielectric layer 88′; abutting or slightly overlapped withdielectric layer 88′.

FIGS. 26-31 are cross-section views illustrating the process flow forforming a field effect transistor 144 shown in FIG. 31 wherein asacrificial metal layer 118 formed to protect a carbon-basednanostructure layer 116 is at least partially reacted with the source120 and drain 122. Reacted residual regions 126 and 128 are designed tohave a greater resistance to the etching process used to removesacrificial metal layer 118 than the unreacted residual regions 43 and47 of FIGS. 21-23.

Referring to FIG. 26, an insulating substrate 16 is shown having apatterned carbon-based nanostructure layer 116, and a patternedsacrificial metal layer 118 on the upper surface 119 of patternedcarbon-based nanostructure layer 116. Source 120 has a portionoverlapping patterned sacrificial metal layer 118 and a portionoverlapping insulating substrate 16. Drain 122 has a portion overlappingpatterned sacrificial metal layer 118 and a portion overlappinginsulating substrate 16. The materials chosen for sacrificial metallayer 118, source 120 and drain 122 are selected to provide a chemicalreaction or alloy upon heating to a predetermined temperature.

FIG. 27 shows reacted region 126 formed by sacrificial metal layer 118reacting with source 120. Reacted region 128 is formed by sacrificialmetal layer 118 reacting with drain 122. Source 120 and drain 122 may bePt and sacrificial metal layer 118 may be Pd which react to form a Pt—Pdalloy which would be more resistant to etching than Pd, for example, Pdnot alloyed with Pt. It is expected that such Pt—Pd alloys may be formedby annealing at a temperature of 600-750° C. for a time in the rangefrom 1 to 15 minutes and that sacrificial metal layer of Pd may beselectively removed with respect to Pt and the reacted Pt—Pd alloyregions by etching in, for example, a 10:1 solution of H₂O₂:H₂SO₄ at 65°C. Alternatively, source 120 and drain 122 may comprise Ni or Pd andsacrificial metal layer 118 may comprise Si, in which case the metals Nior Pd would react with Si to form reacted regions comprising thesilicides NiSi_(x) or PdSi_(x). The Ni or Pd and Si choice of materialshas the advantage of a wide process window in that Si readily reactswith Ni and/or Pd before it will react with the carbon-basednanostructure 116. Tetramethylammoniumhydroxide (TMAH) is a wet etchsuitable for removing Si selectively to Pd and Ni and their silicides,though the metals Pd and Ni are expected to be less resistant to TMAHthan their silicides.

FIG. 28 is a cross-section view after sacrificial metal layer 118 isetched away. FIG. 29 shows a gate dielectric 134 formed over thestructure 132 of FIG. 28. FIG. 30 shows openings 136 and 138 formed ingate dielectric 134 to expose the upper surface of source 120 and drain122. FIG. 31 shows field effect transistor 144 with gate electrode 142formed over gate dielectric 134. Openings 136 and 138 may remain open asshown in FIG. 31 or openings 136 and 138 may be processed to form anelectrical contact to source 120 and drain 122 by filling openings 136and 138 with a conductor.

FIGS. 32-37 are cross-section views illustrating the process flow forforming field effect transistor 178 shown in FIG. 37 with a multilayersource 150 and drain 152 comprising a conductive diffusion barrier layer156 sandwiched between an upper metallic layer 158 and a lower reactivelayer 154 which may be insulating, where the conductive diffusionbarrier layer 156 functions to ensure that the lower reactive layer 154reacts only with patterned sacrificial metal layer 118 and not with theupper metallic layer 158. Referring to FIG. 32, an insulating substrate16 is shown having a patterned carbon-based nanostructure layer 116, anda patterned sacrificial metal layer 118 on the upper surface 119 ofpatterned carbon-based nanostructure layer 116. Main metallic layer 158is selected to have a high conductivity. As mentioned above, conductivediffusion barrier 156 functions to ensure that reactive layer 154 reactsonly with patterned sacrificial metal layer 118 and not with main metallayer 158.

FIG. 33 shows reacted region 160 formed by sacrificial metal layer 118reacting with insulating reactive layer 154 of source 150. Reactedregion 162 is formed by sacrificial metal layer 118 reacting withreactive layer 154 of drain 152. Materials selected may be Ni forpatterned sacrificial metal layer 118, Si for reactive layer 154, TiNfor conductive diffusion barrier 156, NiSi_(x) for reacted regions 160and 162, and Pd for main metal layer 158. The above materials have theadvantage that Ni+Si reactions occur in the range from 300° C. to 400°C. Reactions between Ni and C would not be expected to occur until thetemperature is above 600° C. Another advantage is the availability ofetchants that can etch Ni selectively with respect to Pd and NiSi_(x),for example, chromium etchants CR-7 and CR-14 (aqueous mixtures of(NH₄)₂Ce(NO₃)₆ with HClO₄ or acetic acid) from Cyantek Corporation, 3055Osgood Court, Fremont, Calif. 94538.

FIG. 34 is a cross-section view of structure 168 after sacrificial metallayer 118 is etched away. FIG. 35 shows a gate dielectric 170 formedover structure 168 of FIG. 34. FIG. 36 shows openings 172 and 174 ingate dielectric 170 to expose the upper surface of main metal layer 158of source 150 and drain 152. FIG. 37 shows field effect transistor 178with gate electrode 180 formed over gate dielectric 170. Openings 172and 174 may remain open as shown in FIG. 37 or openings 172 and 174 maybe processed to form an electrical contact to source 150 and drain 152by filling openings 172 and 174 with a conductor.

FIGS. 38-43 are cross-section views illustrating the process for formingfield effect transistor 202 shown in FIG. 43 with additional topsource/drain dielectric layer 186 and 188 and reacted channel-protectresiduals 190 and 192. Referring to FIG. 38, an insulating substrate 16is shown having a patterned carbon-based nanostructure layer 116, and apatterned sacrificial metal layer 118 on the upper surface 119 ofpatterned carbon-based nanostructure layer 116. Source 182 and drain 184comprise a reactive layer such as amorphous Si or poly Si. Amorphous Simay be preferred over poly Si because amorphous Si can be deposited witha lower thermal budget i.e. at a lower temperature and reacted to formsilicides, for example, with Ni. Above source 182 is a dielectric layer186 which may be a self aligned insulator, for example, SiN. Above drain184 is a dielectric layer 188 which may be a self aligned insulator, forexample, SiN. Dielectric layers 186 and 188 function to reduce thecapacitance between gate electrode 204 shown in FIG. 43 to be formed andsource 182 and drain 184.

FIG. 39 shows reacted region 190 formed by sacrificial metal layer 118reacting with source 182. Reacted region 192 is formed by sacrificialmetal layer 118 reacting with drain 184. Materials selected may be Ni orPd for patterned sacrificial metal layer 118, amorphous Si or poly Sifor source 182 and drain 184, and NiSi for reacted regions 190 and 192.The above materials have the advantage that Ni+Si reactions occur in therange from 300° C. to 400° C. Reactions between Ni and C would not beexpected to occur until the temperature is above 600° C. Theconductivity of source 182 and drain 184 does not matter much as long asreacted regions 190 and 192 are large enough for contact with sourceelectrode 206 and drain electrode 208, respectively, shown in FIG. 43.

FIG. 40 is a cross-section view of structure 194 after sacrificial metallayer 118 is etched away. FIG. 41 shows a gate dielectric 196 formedover structure 194 of FIG. 40. FIG. 42 shows openings 197 and 198 ingate dielectric 196 and dielectric layers 186 and 188 respectively toexpose the upper surface of reacted regions 190 and 192, source 182 anddrain 184. FIG. 43 shows field effect transistor 202 with gate electrode204 formed over gate dielectric 196, a source electrode 206 formed inopening 197 and a drain electrode 208 formed in opening 198.

In alternate embodiments, insulating substrate 16 shown in FIGS. 1-43may include embedded bottom gates and bottom gate dielectrics fabricatedby methods known to the art. FIGS. 44 and 45 show cross-section views ofrespective exemplary bottom gated field effect transistors 214 and 215incorporating a carbon based nanostructure layer 116 and FIGS. 46-47show cross-section views of respective exemplary double-gated fieldeffect transistors 216 and 217 incorporating a carbon basednanostructure layer 116. In FIGS. 44-47, embedded bottom gates 240 andbottom gate dielectrics 242 and 244 are positioned under carbon basednanostructure layer 116 such as graphene and/or carbon nanotubes. Bottomgate dielectric 244 may be localized to or patterned to cover respectivebottom gate 240 as shown in FIGS. 45 and 47. Bottom gate dielectric 242may extend beyond respective bottom gate 240 and may extend beyondcarbon-based nanostructure layer 116 and over a portion of insulatingsubstrate 16 as shown in FIGS. 44 and 46.

The device structures of FIGS. 44-47 include source 248, drain 250 andchannel-protect residuals 252 and 254, formed according to the methodsdescribed in the earlier figures such as FIGS. 29 and 31.Channel-protect residuals 252 and 254 may be as deposited or unreactedor reacted with a sacrificial metal layer as described above and shownin FIGS. 26-28. The device structures of FIGS. 44 and 45 show apassivating/protection layer 258. FIGS. 44 and 45 show bottom-gatedfield effect transistors 214 and 215 incorporating insulatingpassivating/protection layer 258 on carbon-based nanostructure layer116. Insulating passivating/protection layer 258 may be localized tocarbon-based nanostructure layer 116, or, as shown in FIGS. 44 and 45,extend beyond carbon-based nanostructure layer 116 over source 248 anddrain 250. FIGS. 46 and 47 show double-gated field effect transistors216 and 217 incorporating top gate dielectric 260 and top gate 262.Additional dielectric layers shown in FIGS. 21-23 may be incorporated intransistors 214-217 shown in FIGS. 44-47.

In FIGS. 2-47, like references are used for functions and apparatusillustrated or shown in an earlier Figure.

While there has been described and illustrated a method for forming Halleffect devices and field effect transistors incorporating a carbon-basednanostructure layer and utilizing a sacrificial metal layer thereover toprotect the carbon-based nanostructure layer during processing, it willbe apparent to those skilled in the art that modifications andvariations are possible without deviating from the broad scope of theinvention which shall be limited solely by the scope of the claimsappended hereto.

1-18. (canceled)
 19. A method for forming a device structure comprising: selecting an insulating substrate having a carbon-based nanostructure layer on an upper surface; forming a first layer of a first metal on said carbon-based nanostructure layer; forming a first patterned layer having a first pattern on said first layer of a first metal; transferring said first pattern to said first layer of a first metal and said carbon-based nanostructure layer to form a first patterned layer of a first metal and a first patterned carbon-based nanostructure layer there under; removing said first patterned layer; forming a layer of first material over said insulating substrate and said first patterned layer of a first metal, said layer of first material reactive with said first patterned layer of a first metal when raised to a predetermined temperature; forming a layer of second material over said layer of first material; said layer of second material providing an electrically conductive diffusion barrier with respect to said layer of first material; forming a second layer of metal over said layer of second material; patterning said layer of first material, layer of second material and said second layer of metal to form source and drain regions spaced apart wherein respective regions have a portion on said patterned metal and a portion on said insulating substrate; heating said layer of first material on said patterned metal to cause a reaction there between for forming a reacted region of one of a chemical compound and an alloy; and selectively removing un-reacted patterned metal to expose said patterned carbon-based nanostructure layer between said source region and said drain region.
 20. The method of claim 19 wherein said carbon-based nanostructure layer is selected from the group consisting of carbon-nanotubes and graphene.
 21. The method of claim 19 wherein said first metal includes metal selected from the group consisting of Ni, Pd, amorphous silicon and polysilicon.
 22. The method of claim 19 wherein forming said layer of second material is omitted.
 23. The method of claim 19 further including: forming a dielectric layer over said exposed patterned carbon-based nanostructure layer, sidewalls of said reacted region, sidewalls of said layer of second material, sidewalls of said second layer of metal and upper surface of said second layer; forming a third layer of metal over said dielectric layer; and patterning said third layer of metal to form an electrode on said dielectric layer over said regions of patterned carbon-based nanostructure layer located between said drain and source regions.
 24. The method of claim 19 wherein said forming a layer of second material provides an insulator in place of a conductive diffusion barrier; wherein forming a second layer of metal over said layer of second material is deleted and wherein patterning said second layer of metal is not performed.
 25. The method of claim 24 further including: forming a dielectric layer over said exposed patterned carbon-based nanostructure layer, sidewalls of said reacted region, sidewalls of said layer of second material, and upper surface of said layer of second material; patterning said dielectric layer and said layer of second material to form openings in said dielectric layer and said layer of second material to said reacted regions and said layer of first material forming a respective source region and drain region; forming a third layer of metal over said dielectric layer and said openings; and patterning said third layer of metal to form a source electrode, drain electrode and gate electrode, said gate electrode on said dielectric layer over said regions of patterned carbon-based nanostructure layer located between said drain and source regions. 